1. Field of the Invention
This invention relates to running a digital signal processor (DSP) at various processing speeds and, more particularly, to determining such processing speeds in accordance with the complexity of tasks to be performed and the capabilities of the particular DSP.
2. Background Information
The processing speed, or MIP rate (million instructions per second) of a DSP is classically chosen according to the access speed of associated memory. However, increases in the circuit density of DSPs has left certain of these devices vulnerable to various other types of functional problems related to their processing speeds. For example, the multiplier function of a particular DSP may work only intermittently at a certain processing speed but reliably at a lower processing speed, with other functions working reliably at both these processing speeds. Such a DSP may be used in an application in which the multiplying function is not addressed, allowing reliable operation at the higher processing speed, or it may be required to run a task requiring use of the multiplying function, so that reliable operation can only be achieved at the lower speed.
DSP chips have been conventionally sorted according to their process speed capability. However, what is needed is a means for establishing a processing speed based both on the capability of an individual chip and on the task to be performed.
One application of DSPs which is particularly sensitive to a need for flexibility in processing speed is that of a DSP-based, time division multiplexing communications adapter connecting a computing system or Internet server to an ISDN transmission line. In such an adapter, DSPs are used for various signal processing operations and for modem emulation. In this environment, an individual DSP may be operating at a relatively slow speed to receive and transmit data on the transmission line, or at a higher speed to process signals, with some signal processing tasks requiring complex functions, such as multiplication.
3. Description of the Prior Art
U.S. Pat. No. 5,260,978 describes a method and apparatus for use with a processor having an ability to operate at different speeds within a predetermined range in response to a recovered timing signal from an ATM telecommunications network.
From The IBM Technical Disclosure Bulletin, Vol. 36, No. 09A, September, 1993, pp. 71-73, an article entitled "Real-Time Operating System for Digital Processors" outlines an operating system for DSPs that provides an efficient multitasking hard real-time environment for concurrent execution of multiple programmable signal processing tasks. Tasks can be dynamically reconfigured without stopping, reducing scheduling overhead for a minor processing overhead. In order to maintain synchrony among a cluster of tasks that are associated with different information sources, having asynchronous information rates, the real-time operating system architecture defines a global real-time clock used for such synchronization.
While these prior art references deal with synchronizing clock speeds and signals in response to varying conditions occurring with differing types of data transmission, a method for dealing with the performance factors determining the process speed at which an individual DSP can be reliably operated is not anticipated. What is needed is a method for determining the process speed in response to the process requirements of particular tasks to be executed and the capability of the individual DSP.